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Mentor Graphics

www.mentor.com

Mentor Graphics, System Level Verification Division

Mentor Graphics and MIPS Technologies work together to create co-verification models for MIPS® cores. These MIPS-specific Seamless® processor support packages (PSPs) enable system developers incorporating the MIPS cores to validate hardware/software interfaces in a virtual prototype prior to fabrication.

As the most broadly based co-verification provider today, Mentor Graphics is committed to providing co-verification solutions for MIPS® processors. The Seamless® solution has been used by engineers around the globe to accelerate time-to-market, improve product quality and reduce the risk of product re-spins.

Verification of the complex interactions between hardware and software is critical to the success of a system-on-chip (SoC) design. Because today's SoCs contain more functionality, functional verification has become the largest design flow bottleneck. Concurrently, functional errors are now the biggest cause of design re-spins. Hardware engineers develop, debug and verify their designs with HDL simulators. Software engineers use compilers, debuggers and Instruction Set Simulators (ISS) to develop software. It is natural to integrate these two environments in order to create a hardware/ software verification and debug tool.

Design teams need co-verification tools that allow the hardware and software engineers to work in tandem, providing more insight into how these two domains work together. This insight, along with the trading of information, enables the hardware and software teams to identify problems and improvements very early in the design flow. Not only are problems easier and faster to fix at this stage, but the criteria for deciding where to make changes (i.e., hardware versus software) is based on what is optimal, not what is convenient.

Enabling decision-making of this sort shortens development time and has enormous impact on the quality of the final design. The leading solution of this kind is the Seamless® Co-Verification environment from Mentor Graphics.

Seamless and MIPS cores

Mentor Graphics and MIPS Technologies work together to create co-verification models for MIPS cores. These MIPS-specific Seamless processor support packages (PSPs) enable system developers incorporating the MIPS cores to validate hardware/software interfaces in a virtual prototype prior to fabrication.

To guarantee the integrity and accuracy of these models, MIPS Technologies provides the ISS and bus functional models from which the Seamless PSPs are developed. These models are integrated with XRAY to provide debugger access to all the critical internals of MIPS CPUs, such as registers, MMU, assembly and source code, memory, stack and function trace. The Seamless environment then links the PSP to the logic simulator used in the hardware verification process, thus providing complete virtual representation of the design.

Currently, the breadth of MIPS processor models supported by the Seamless kernel include the MIPS32® 4K®, 4KE™, 4KS™ 24K® and 24KE™ , 34K™ and MIPS64® 5K® and 20Kc™ families. Seamless also offers PSPs for processors developed by MIPS licensees, such as PMC-Sierra, LSI Logic and Toshiba.

Seamless Optimizations

The "optimization" technology of Seamless allows developers to run large amounts of software in their simulation environment. For example, it is almost inconceivable to boot and run an RTOS within a logic simulation environment, but this is done in a matter of minutes within Seamless.The performance gains to be had via Seamless optimizations can be seen in a recent customer application. The customer design booted a Linux operating system on a MIPS64 20Kc™ core. Without the Seamless memory optimizations, 16.8 million instructions would take 9.7 days to execute. When Seamless memory optimizations were applied, the operating system booted up in 9 minutes, 15 seconds. This calculates to a simulation speed of about 30,000 instructions per second with optimizations on. Only 20 instructions per second were achieved without Seamless optimizations.The customer's procedure was to simulate enough of the boot-up with the Seamless memory optimizations disabled to verify that their memory subsystem was working. Then they turned on the optimizations to get through the boot-up process at an extremely rapid rate. This allowed them to move on to verification of the device drivers and some application code - i.e., true system simulation - very early and quickly.

Performance Analysis Capability

New features have expanded Seamless to now collect code execution, memory transaction and bus utilization data. This data is then graphically displayed for visualization of system performance. The Performance Profile Viewer (PPV) gives insight into components that influence system performance. PPV gives insight into cache effectiveness, bus bandwidth and bottlenecks, interrupt responsiveness and code profiling.