MIPS Products

MIPS® MT ASE

Multithreading, or the concurrent presence of multiple active threads on the same CPU, is a technique for tolerating memory and execution latency and getting higher utilization out of processor functional units. This technique popularized by Intel is also known as Hyper-Threading. A processor pipeline can achieve 80-90% utilization by switching threads during data-dependent stalls or cache misses. The MIPS MT ASE provides a framework for multithreading the MIPS architecture.

Related Links: 34K - 1004K

  • Multi-threading is an execution model that is geared towards maximizing throughput within a system
  • Allows multiple software threads to consume all execution and memory bandwidth instead of stalling within one software thread
  • Two MT modes supported:
    • Multiple Virtual Processors, which allows multiple operating systems to be simultaneously running on physical CPU
    • Multiple Thread Contexts, in which multiple threads of a single software process can be simultaneously running on one physical CPU
  • Quality of service (QoS) scheduling satisfies real-time requirements
  • Threads are relocate-able in multi-core systems
  • Immediate system throughput boost of 20-40% with little or no code changes
  • TCs (Thread Context) replicate user-mode state such as the general purpose registers
  • VPEs (Virtual Processor Elements) replicate privileged-mode state such as the TLB and status registers pertaining to interrupts
  • Multiple TCs can be assigned to any VPE
  • Switching among runnable threads is handled by hardware
    • Fine-grained switching between threads is possible, including switching every CPU cycle
    • Thread switching policy is totally customer defined - can be round-robin, weighted-round-robin, priority-driven, etc.
  • Software controls the creation as well as the suspension of runnable threads
  • Support for hardware events (such as interrupts) to suspend or wake up threads
  • Gating storage can be used as a communications channel between threads - allows for data-driven scheduling of threads
  • A thread can be marked as privileged to allow access to another thread's resources
  • Interrupt affinity to a specific VPE is supported
  • Software control is provided for enabling and disabling of each TC and VPE

See MIPS Run, Second Edition
Author: Sweetman, Dominic
Publisher: Morgan Kaufmann; 2 edition (October 31, 2006)
ISBN-10: 0120884216
ISBN-13: 978-0120884216

MIPS Assembly Language Programming
Author: Britton, Robert
Publisher: Prentice Hall; illustrated edition edition (June 7, 2003)
ISBN-10: 0131420445
ISBN-13: 978-0131420441

The Mips Programmer's Handbook
Author: Bunce, Philip; Farquhar, Erin
Publisher: Morgan Kaufmann; 1st edition (January 15, 1994)
ISBN-10: 1558602976
ISBN-13: 978-1558602977

Real-Time Embedded Multithreading Using ThreadX and MIPS
Author: Lamie, Edward
Publisher: Newnes; Pap/Cdr edition (December 26, 2008)
ISBN-10: 1856176312
ISBN-13: 978-1856176316

Computer Architecture, Fourth Edition: A Quantitative Approach
Authors: Hennessy, John; Patterson, David
Publisher: Morgan Kaufmann; 4 edition (September 27, 2006)
ISBN-10: 0123704901
ISBN-13: 978-0123704900