MIPS Products

MIPS32® 24K® Family

Take advantage of the highest performance 32-bit cores in the embedded industry while minimizing design time and reducing product costs. Tailored SoC design methodologies, an Open Core Protocol (OCP) interconnect structure, standard libraries and on-chip memories from industry-leading companies ensure that products based on 24K cores are brought to marketwith speed, ease and efficiency.

Designed to power through graphics, Java and demanding code and with features like an ultrafast multiply, intelligent caches, floating point support and the CorExtend™ capability - which allows users to supercharge application performance by defining and adding their own instructions - the 24K family is the ideal solution for digital and interactive television, set-top boxes, DVD and other performance-driven applications.

  • An 8-stage pipeline and up to 730-MHz performance, enables SoC designers to reduce product costs and speed time-to-market by giving them the performance headroom to implement more features now and upgrades in the future with software flexibility rather than rigid, fixed hardware.

  • Extensive EDA Tools Support (Cadence, Synopsys, Magma, Mentor)

  • By standardizing the core interface on OCP (www.ocpip.org), the 24K core accelerates time-to-market by enabling easy reuse of standard SoC IP. Memory controllers, bus interconnects and other standardized peripherals are now easily integrated through common on-chip interfaces.

  • The 24K family is based on the highly scalable 24K microarchitecture, which features enhancements to the industry-standard MIPS32 architecture, enhanced bit-field manipulation, reduced interrupt latency and enhanced cache control.

  • Rich environment of third-party tools and software support.



32-bit MIPS32® architecture

  • 8-stage pipeline
  • 32-bit address
  • 64-bit data paths to caches and external interface
  • Vectored interrupts and support for external interrupt controller
  • GPR shadow registers (optionally, one or three additional shadows can be added to minimize latency for interrupt handlers)

Programmable cache size

  • Individually configurable instruction and data caches, sizes of 16KB, 32KB and 64KB
  • 4-way set-associative
  • Up to four outstanding non-blocking loads
  • Write-back and write-through support
  • 32-byte cache line size

Scratch pad data ram support

  • Independent of data cache configuration
  • 64-bit OCP interface for external access, DMA
  • Can support arrays up to 1 MB
  • Interface allows back-stalling the core pipeline

Memory-management unit (MMU)

  • 4 entry instruction TLB
  • 8 entry data TLB
  • Configurable 16/32/64 dual-entry joint TLB with variable page sizes
  • Optional fixed mapping translation (FMT) for applications not requiring address mapping or protection

Bus Interface Unit (BIU)

  • Implements the Open Core Protocol (OCP Release 2.x)
  • 64-bit read and write data buses to efficiently transfer data between memory and L1 caches
  • Supports a variety of core/bus clock ratios to give greater flexibility for system implementations (1, 1.5, 2, 2.5, 3, 3.5, 4 or 5)
  • 4 entry write buffer

Integer multiply/divide unit (MDU)

  • Fully pipelined single-cycle repeat rate for 32X32 MAC instructions

Power control

  • Minimum frequency: 0 MHz
  • Power-down mode (triggered by WAIT instruction)
  • Support for software-controlled clock divider
  • Support for extensive use of local gated clocks

EJTAG debug

  • Support for single stepping
  • Virtual instruction and data address breakpoints
  • PC and data tracing

General purpose coprocessor (COP 2) interface

  • 64-bit interface to a user defined coprocessor

Reference Flows

  • Complete front to back reference flows for Cadence, Magma and Synopsys



Process65GP TSMC
Frequency - worst case730 MHz
Performance1.55 DMIPS/MHz
Power Consumption0.21
Core Size0.83 mm2 (core only, extracted from fully layed out GDSII database)
Note: Frequency, power consumption and size depend upon configuration options, synthesis, silicon vendor, process and cell libraries.




24Kc™ Core: This base core includes a high-performance 32x32 multiply/divide unit and configurable MMU with TLB or fixed mapping.

24Kf™ Core: Adds hardware floating point support that is fully compliant with IEEE 754.

24K® Pro Cores: 24Kc Pro and 24Kf Pro cores feature the CorExtend™ capability.