MIPS64® Architecture
The MIPS64® architecture sets a new performance standard for 64-bit MIPS-Based™ embedded processors. It represents the foundation for next generation high-performance MIPS® processors and provides upward compatibility to the MIPS32® 32-bit architecture. The MIPS architecture is the leading embedded processor technology because of its robust instruction set, scalability from 32-bits to 64-bits, availability of software development tools, and widespread support from numerous MIPS Technologies licensees. The MIPS64 architecture is a superset of the previous MIPS IV™ and MIPS V™ Instruction Set Architectures (ISAs) and incorporates powerful new instructions specifically for embedded applications as well as proven memory management and privileged mode control mechanisms previously implemented in R4000® and R5000® MIPS processors. By incorporating powerful new features, standardizing privileged mode instructions, supporting past ISAs, and providing an upgrade path from the MIPS32 architecture, the MIPS64 architecture provides a solid high-performance foundation for future MIPS processor-based development.The MIPS64 architecture is based on a fixed-length, regularly encoded instruction set, and it uses a load/store data model. It is streamlined to support optimized execution of high-level languages. Arithmetic and logic operations use a three-operand format, allowing compilers to optimize complex expressions formulation. Availability of 32 general-purpose registers enables compilers to further optimize code generation by keeping frequently accessed data in registers.
The architecture derives the privileged mode exception handling and memory management functions from the R4000 and R5000 class processors. A set of registers reflects the configuration of the caches, MMU, TLB, and other privileged features implemented in each core. A MIPS32 architecture compatibility mode allows running 32-bit code on the MIPS64 without changes. By providing backwards compatibility, standardizing privileged mode, and memory management and providing the information through the configuration registers, the MIPS64 architecture enables real-time operating systems and application code to be implemented once and reused with future members of both the MIPS32 and the MIPS64 processor families.
Flexibility of high-performance caches and memory management schemes continues to be a strength of the MIPS architecture. The MIPS64 architecture extends this advantage with well-defined cache control options. The size of the instruction and data caches can range from 256 bytes to 4Mbytes. The data cache can employ either a write-back or write-through policy. A no-cache option can also be specified. The memory management mechanism can employ either a TLB or a Block Address Translation (BAT) policy. With a TLB, the MIPS64 architecture meets Windows® CE and Linux memory management requirements.
The addition of data streaming and predicated operations supports the increasing computation needs of the embedded market. Conditional data move and data prefetch instructions are standardized, allowing for improved system-level data throughput, in communication and multimedia applications.
Fixed-point DSP-type instructions further enhance multimedia processing. These instructions that include Multiply (MUL), Multiply and Add (MADD), Multiply and Subtract (MSUB), and "count leading 0s/1s," previously available only on some 64-bit MIPS processors, provide greater performance in processing data streams such as audio, video, and multimedia without adding additional DSP hardware to the system.
Powerful 64-bit floating-point registers and execution units speed the tasks of processing some DSP algorithms and calculating graphics operations in real-time. Paired-single instructions pack two 32-bit floating-point operands into a single 64-bit register, allowing Single Instruction Multiple Data operations (SIMD). This provides twice as fast execution compared to traditional 32-bit floating-point units. Floating point operations can optionally be emulated in software.
The MIPS64 architecture features both 32-bit and 64-bit addressing modes, while working with 64-bit data. This allows reaping the benefits of 64-bit data without the extra memory needed for 64-bit addressing. In order to allow easy migration from the 32-bit family, the architecture features a 32-bit compatibility mode, in which all registers and addresses are 32-bit wide and all instructions present in the MIPS32 architecture are executed.
Features
- 64-bit MIPS® RISC processor instruction set with R4000® and R5000® TLB and privileged mode extensions.
- Fully MIPS IV™ and MIPS V™ ISA compatible
- Standardized DSP operations: multiply (MUL), multiply and add (MADD), and count leading 0/1s (CLZ/O)
- Privileged cache load/control operations
- Two addressing modes for embedded systems optimization:
- 32-bit addressing and 64-bit data (retaining MIPS32® addressing)
- Full 64-bit address and data operation (MIPS IV and MIPS V ISA compatible)
- Backward compatible with MIPS32; 32-bit architecture standard
- Robust load/store RISC instruction set with 3-operand instructions in most formats (3 register, 2 registers + immediate), branch/jump options, and delayed jump instructions.
- 32 general purpose 64-bit registers (GPRs)
- Two multiply/divide registers (HI and LO)
- Optional floating point support
- 32 double precision 64-bit floating point registers (FPRs)
- Floating point condition code register
- Optional paired single-precision floating-point instruction execution (SIMD)
- Optional Memory Management Unit with:
- TLB or BAT address translation mechanisms
- Programmable page size
- Optional Caches:
- Instruction and or data cache options
- Write-back or write-through data-cache options
- Virtual or physical addressing
- Enhanced JTAG (EJTAG) support for non-intrusive debug support
