24KEc® Hard IP Cores
The MIPS32® 24KEc® Hard IP Cores are technology-specific implementationsof the synthesizable 32-bit MIPS32 24KEc core. Available implementation targetsinclude TSMC 0.13µm CL013G process. Chip developers or system OEMs whoare building complex System-On-Chip (SoC) ASIC devices can significantly reducedesign time, resources, and time to-market by using 24KEc Hard IPCores.- Hard IP cores allow designers to significantly reduce design time, efficiently use resources, and quickly get to market
- Based on MIPS32 architecture for high performance
- 16KB Instruction and 16KB writeback Data cache for more flexibility and higher performance
- Instruction and data scratchpad interfaces available
- A coprocessor 2 (COP2) interface enables easy coprocessor connection and support
- Extensive clock gating reduces power consumption without reducing application performance
- Enhanced JTAG (EJTAG) debug with trace and fast download enable quick and easy debugging
- All major operating systems and compiler tool chains, and hundreds of third-party development tools, support the MIPS architecture
- Testability features include BIST and full scan
- Supports CorExtend capability which enables users to significantly enhance the value and competitive advantage of their SoC products
Hard Microprocessor Cores
- 333 MHz in TSMC .13µm process
- 476 MHz in TSMC 90G process
32-bit MIPS32 enhanced architecture
- 32-bit address and data paths
- Memory management unit with TLB
- Bit field instructions
- Vectored interrupts
Memory-management unit
- 32 dual-entry JTLB
Fixed Caches
- 16K/16K instruction and data caches
- 4-way set-associative
- Write-back or write-through
Integer multiply/divide unit
- Fast MDU
- Maximum issue rate of one 32x32 multiply per clock
- Scratchpad Interface
General purpose coprocessor (COP2) interface
- 32-bit interface to an external coprocessor
Power control
- Minimum frequency: 0 MHz
- Power-down mode (triggered by WAIT instruction)
- Support for extensive use of local gated clocks
EJTAG debug
- Support for single stepping
- Virtual instruction and data address breakpoints
Development support
- MIPS® SDE GNU based toolchain, MIPSsim™ Instruction Set Simulator, MIPS DSP Library. These tools are licensed for Windows, Linux and Solaris operating systems
- A complete offering of third-party development tools.
| Process | 0.13µm TSMC | 90G TSMC |
| Frequency* | 333 MHz1 | 476 MHz |
| Core Size | 4.33 sq. mm including caches2 | 2.4 mm(2) including caches |
*Frequency measured under worst case conditions (SS process corner,Vdd nom - 10%, Tj=125oC) and with perfect input clock 216K/16K caches
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