MIPS Products

System Navigator™ Probe
for Altera Nios II Embedded Processors


The System NavigatorTM probe for Altera NIOS II Embedded Processors is designed to support the special features and integrated peripherals of the Altera Nios II cores embedded in Altera FPGA devices.

The Nios II processor cores feature a configuration option to include On-Chip Instrumentation (OCI®) debug logic in the design. The OCI logic provides powerful trace, triggering, and performance analysis features for faster and easier system and software debug and testing.

The table below shows the various options available to the Nios II FPGA designer.

The System Navigator probe supports on-chip trace capture. It has a USB 2.0 and 10/100 Ethernet interface to the PC host. It uses a 10-pin JTAG debug connector for the target interface. It runs on Windows® 2000/XP PCs.

Product / Feature Table

Key Features

USB Blaster
with Nios II
Kit

Software Feature
Upgrade

SNAV-NIOS II-ETH
Probe

Execution Breakpoints

2

4

4

Data/Cycle Breakpoints (Note 1)

2

4

4

Trace Depth (Note 2)

16 Frames

Unlimited

Unlimited

Data/Bus Cycle Trace

No

Yes

Yes

Source-level Debug

Yes

Yes

Yes

Performance Analysis

No

Yes

Yes

Host Connection

USB Blaster

USB Blaster

USB 2.0
10/100 Ethernet

Target Connector

JTAG

JTAG

JTAG

Notes:
(1) Set trigger on address/address range, data values, with masking support, and/or on cycle types
(2) Limited only by RAM resources on-chip

Key Features
  • Supports Altera Nios II core with On-Chip Instrumentation (OCI) debug extensions
  • On-chip trace supported
  • Real-time execution trace
  • Data and bus cycle trace
  • Trace can be gated on/off by on-chip triggers
  • Configurable trace options: instructions only, data cycles only, or both
  • Max trace depth limited by Nios II processor configuration
  • Unlimited software breakpoints
  • Up to 8 hardware breakpoints (4 instruction/4 data)
  • Go, halt processor run control
  • Single-step by assembly or C source line
  • Read-write all CPU registers and memory
  • Flash programming support
  • Debug of multiple Nios II cores supported
  • Low-level access to JTAG functions for verification
  • Single line assembler and disassembler
  • Command-line interface with Tcl/tk scripting language standard
  • Source-level debug supported